dsPIC33F General Purpose Digital Signal Controller (DSC) with seamless migration options to PIC24F, PIC24H MCUs and dsPIC30F DSCs in similar packages.

 

Parameter Name	Value
Architecture	16-bit
CPU Speed (MIPS)	40
Memory Type	Flash
Program Memory (KB)	256
RAM Bytes	30,720
Temperature Range C	-40 to 85
Operating Voltage Range (V)	3 to 3.6
I/O Pins	85
Pin Count	100
System Management Features	PBOR
Internal Oscillator	7.37 MHz, 512 kHz
nanoWatt Features	Fast Wake/Fast Control
Digital Communication Peripherals	2-UART, 2-SPI, 2-I2C
Analog Peripherals	2-A/D 32x12-bit @ 500(ksps)
CAN (#, type)	2 ECAN
Capture/Compare/PWM Peripherals	8/8
16-bit PWM resolutions	16
Timers	9 x 16-bit 4 x 32-bit
Parallel Port	GPIO
Hardware RTCC	No
DMA	8

Operating Range:
DC – 40 MIPS (40 MIPS @ 3.0-3.6V, -40°C to +85°C)
Industrial temperature range (-40°C to +85°C)
High-Performance DSC CPU:
Modified Harvard architecture
C compiler optimized instruction set
16-bit wide data path
24-bit wide instructions
Linear program memory addressing up to 4M instruction words
Linear data memory addressing up to 64 Kbytes
83 base instructions: mostly 1 word/1 cycle
Sixteen 16-bit General Purpose Registers
Two 40-bit accumulators:
- With rounding and saturation options
Flexible and powerful addressing modes:
- Indirect, Modulo and Bit-Reversed
Software stack
16 x 16 fractional/integer multiply operations
32/16 and 16/16 divide operations
Single-cycle multiply and accumulate:
- Accumulator write back for DSP operations
- Dual data fetch
Up to ±16-bit shifts for up to 40-bit data
Direct Memory Access (DMA):
8-channel hardware DMA:
2 Kbytes dual ported DMA buffer area (DMA RAM) to store data transferred via DMA:
- Allows data transfer between RAM and a peripheral while CPU is executing code (no cycle stealing)
Most peripherals support DMA
Interrupt Controller:
5-cycle latency
118 interrupt vectors
 dsPIC33FJXXXGPX06/X08/X10 Data Sheet