|
Parameter Name
|
Value
|
|
Architecture
|
16-bit
|
|
CPU Speed (MIPS)
|
40
|
|
Memory Type
|
Flash
|
|
Program Memory (KB)
|
256
|
|
RAM Bytes
|
30,720
|
|
TemperatureRange C
|
-40 to 85
|
|
Operating VoltageRange (V)
|
3 to 3.6
|
|
I/O Pins
|
85
|
|
Pin Count
|
100
|
|
System Management Features
|
PBOR
|
|
Internal Oscillator
|
7.37 MHz, 512 kHz
|
|
nanoWatt Features
|
Fast Wake/Fast Control
|
|
Digital Communication Peripherals
|
2-UART, 2-SPI, 2-I2C
|
|
Analog Peripherals
|
2-A/D 24x12-bit @ 500(ksps)
|
|
CAN (#, type)
|
2 ECAN
|
|
Capture/Compare/PWM Peripherals
|
8/8
|
|
16-bit PWM resolutions
|
16
|
|
Motor Control PWM Channels
|
8
|
|
Quatrature Encoder Interface (QEI)
|
1
|
|
Timers
|
9 x 16-bit 4 x 32-bit
|
|
ParallelPort
|
GPIO
|
|
Hardware RTCC
|
No
|
|
DMA
|
8
|
Operating Range:
# DC – 40 MIPS (40 MIPS @ 3.0-3.6V, -40°C to +85°C)
# Industrial temperature range (-40°C to +85°C) High-Performance DSC CPU:
# Modified Harvard architecture
# C compiler optimized instruction set
# 16-bit wide data path
# 24-bit wide instructions
# Linear program memory addressing up to 4M instruction words
# Linear data memory addressing up to 64 Kbytes
# 83 base instructions: mostly 1 word/1 cycle
# Sixteen 16-bit General Purpose Registers
# Two 40-bit accumulators: - With rounding and saturation options
# Flexible and powerful addressing modes: - Indirect, Modulo and Bit-Reversed
# Software stack